DIP CD4023BE CD4023 Gate / Inverter / Logic NAND Gate Chip

The CD4023  DIP14 CMOS NAND Gates, provide the system designer with direct implementation of the positive-logic NAND function and supplement the existing family of CMOS gates.

• Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
• 100% tested for quiescent current at 20 V
• The maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
  1 V at V_DD = 5 V
  2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of  CMOS Devices"